A 12-bit 2.32 GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer

This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR architecture dual-channel sampling multiplying digital-to-analog (MDAC) and one shared flash sub-ADC used exploiting simple calibration. The ADC achieves signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB spurious-free-dynamic-range (SFDR) 72.18dB 1125MHz consumes 175 mW.